Customising Cypress FX3™ SuperSpeed Explorer Kit to work with high-end Xilinx boards.

There is a beautiful development kit from Cypress, called USB3  SuperSpeed  explorer kit that allows jump-start developing USB3 hardware and software.Together with FMC Interconnect board for Xilinx dev. kits, also from Cypress, it opens the door for  previously unseen amazing ~320 MBytes per second data transfer rate to/from the FPGA to  PC. And yes, the price of each board is ~50$. There is, however one “small” problem: The kit is designed for low-end Spartan 6 development board, that uses 3.3 volts for digital input-outputs. This “small” problem makes the kit useless if one wants to interface mid-high level boards with more then one FMC connector. Actually most use-cases need more then one FMC slot to take advantage of the amazing 320 Mytes/sec speed: The first FMC is the actual FX3  board and the second one is the interface under the interest: it can be video receiver/transmitter, fast DAC or ADC or GBits range network interface/s.

There is, however a simple solution to make the FX3 dev kit to work with a 2.5 or 1.8 Volt digital IO based Xilinx boards. Looking at the relevant part of the schematics: of the FX3 dev. kit:

USB3_VRegThere is  NCP1117DT33RKG voltage regulator that supplies 3.3 volts  to digital IO pins of the USB3 FX3 chip. The good thing is that it can be replaced with 1.8  or 2.5 Volts regulators, from the same manufacturer and with the same form factor. The 1.8 Volt solution was tested and worked fine with VC707 board from Xilinx (Virtex 7 FPGA) . The 2.5 Volt regulator was tested with KC705 board from Xilinx (Kintex 7) FPGA.

The part number for 1.8 volt regulator is NCP1117DT18RKG

The part number for 2.5  volt regulator is NCP1117DT25RKG

In the picture below the part to be replaced is circled in red. That’s it, all the IO pins of the FX3 that were 3.3 Volts will become 1.8/2.5 Volts depending on the selected regulator part number.


 Validating FX3 I2C communication to configure ADV7619 4k HDMI receiver:


Validating 32 bit data bus clock at 80 MHz:  (More about the signal integrity on the separate post)


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